One of the built-in integrated semiconductor storage devices of an LSI is nonvolatile memory. This memory is very important in order to use the LSI in various applications, since it can retain stored data even after power to the LSI is removed.
Nonvolatile semiconductor memory devices employing a floating gate or an insulating film are described in, for example, S. Sze, “Physics of Semiconductor Devices”, 2nd edition, Wiley-Interscience pub., p. 496-506 (Nonpatent Document 1). As is known in the art, unlike floating-gate nonvolatile memory, the type of nonvolatile memory in which an insulating film is laminated to store charges in the traps at the interface and in the insulating film does not require an additional conductive layer and hence can be formed in a manner matching the CMOS LSI process. However, this type of nonvolatile memory in which charges are retained within the insulating film must maintain sufficient charge retention characteristics while injecting or releasing charge, which is difficult to practically achieve.
On the other hand, it has been proposed that charge of opposite polarity may be injected to rewrite the stored data, instead of releasing the retained charge. The operation of such a nonvolatile memory device is described in 1997 Symposium on VLSI Technology, 1997, p. 63-64 (Nonpatent Document 3). In this memory, each cell includes two separate gates: a polysilicon gate for memory operation and a gate for memory cell selection. Further, similar memory devices are disclosed in U.S. Pat. No. 5,969,383 (Patent Document 1) and U.S. Pat. No. 6,477,084 (Patent Document 2).
In a memory cell structure disclosed in the above documents, two NMOS based transistors, namely a select transistor and a memory transistor, are disposed in a stacked arrangement and connected to each other. An equivalent circuit is shown in FIG. 1C. In FIG. 1C, a select transistor 1 and a memory transistor 2 are connected in series. FIGS. 1A and 1B show a plan view and a cross-sectional view, respectively, of the memory device or cell shown in FIG. 1C. Specifically, FIG. 1A shows the arrangement of a select gate pattern 1500, a memory gate pattern 1550, and an active region pattern 1150 on the substrate of the memory device. FIG. 1B shows a cross-sectional view of the memory device, as described above. Referring to FIG. 1B, a gate 500 of the select transistor (hereinafter referred to as a select gate 500) and a gate 550 of the memory transistor (hereinafter referred to as a memory gate 550) are formed on a semiconductor substrate 100. Diffusion layer electrodes 200 and 300 constituting the electrode portions of the memory device are formed in the semiconductor substrate 100. Further, a spacer insulator 940 is formed on a sidewall of each gate 500, 550, and diffusion layers 310 and 210 are formed in the semiconductor substrate 100. It should be noted that reference numeral 900 denotes the gate insulating film of the select transistor and 950 denotes the gate insulating film of the memory transistor.
According to the present invention, a gate namely, the memory gate may be formed in a process called a spacer process, as shown in FIG. 1B. In this process, after forming the gate 500 of the select transistor, the gate insulating film 950 of the memory gate 550 is formed. Then, after depositing a gate material of the memory gate 550 on the gate insulating film 950, the wafer is anisotropically etched in a direction perpendicular to its surface to form the memory gate 550 on a side of the select gate 500. This process is hereinafter referred to as a spacer process.
There will now be described the operation of a nonvolatile memory device according to the present invention. It should be noted that methods for forming a nonvolatile memory device according to the present invention will be described later in detail in connection with preferred embodiments of the present invention. FIG. 2 shows an array arrangement of memory cells (BIT1, BIT2) each represented by the equivalent circuit shown in FIG. 1C. In FIG. 2, the gates of the select transistors 1 of the first-row memory cells (BIT1, BIT2, and so on) constitute a word line SGL0, and the gates of the memory transistors 2 of the first-row memory cells constitute a word line MGL0; the gates of the select transistors 1 of the second-row memory cells (BIT1, BIT2, and so on) constitute a word line SGL1, and the gates of the memory transistors 2 of the second-row memory cells constitute a word line MGL1; the gates of the select transistors 1 of the third-row memory cells (BIT1, BIT2, and so on) constitute a word line SGL2, and the gates of the memory transistors 2 of the third-row memory cells constitute a word line MGL2; and so on. Further, the diffusion layers of the select transistors 1 of the first-column memory cells (BIT1) constitute a bit line BL0, and the diffusion layers of the memory transistors 2 of the first-column memory cells constitute a source line SL0; the diffusion layers of the select transistors 1 of the second-column memory cells (BIT2) constitute a bit line BL1, and the diffusion layers of the memory transistors 2 of the second-column memory cells constitute a source line SL1; and so on. The first-row memory cells (BIT1, BIT2, and so on) may be denoted collectively by reference numeral WORD1, and the second-row memory cells (BIT1, BIT2, and so on) may be denoted collectively by reference numeral WORD2, as shown in FIG. 2.
FIGS. 3 and 4 are schematic cross-sectional views of a memory cell portion, illustrating exemplary program or write and erase operations on the memory cell. These figures schematically show the memory cell structure and the program and erase operations and do not show the detailed structure. It should be noted that in FIGS. 3 and 4, components common to FIG. 1B are designated by the same reference numerals. The gate insulating film 950 of the memory gate has a structure in which a silicon nitride film is sandwiched between silicon oxide films; that is, it has the so-called MONOS (Metal-Oxide-Nitride-Oxide Semiconductor (silicon)) structure. The gate insulating film 900 of the select gate is a silicon oxide film. The diffusion layer electrodes 200 and 300 are formed using the select gate 500 and the memory gate 550 as masks.
There are 4 basic operations performed on this memory cell: (1) program, (2) erase, (3) retain, and (4) read. It should be noted that although the 4 basic operations are typically called in this way, other terms may be used to refer to them. Further, what is regarded as a program operation in one application may be regarded as an erase operation in another application, and vice versa. Although the following description only refers to exemplary operations, various operations may be performed on this memory cell. Further, although the following description assumes the memory cell to be an NMOS memory cell, it may be a PMOS memory cell (which may be formed and operated in the same manner as the NMOS memory cell).
(1) FIG. 3 schematically shows a program or write operation. A positive potential is applied to the diffusion layer electrode 200 on the memory gate side, and ground potential is applied to the substrate 100 and the diffusion layer electrode 300 on the select gate side. A gate overdrive voltage higher than the voltage of the substrate 100 is applied to the memory gate 550 to set the channel under the memory gate 550 to an “on” state. At that time, the potential of the select gate 500 is set 0.1-0.2 V higher than the threshold voltage to cause the channel to assume the “on” state. As a result, a conductive state is established to allow electrons to move, as shown in FIG. 3. Since in this state the highest electric field is produced around the boundary between the two gates, a number of hot electrons are generated and injected into the memory gate side. It should be noted that in FIG. 3, the white circle under the select gate 500 indicates an electron, a channel electron. This electron is accelerated to become a hot electron which is then injected into the MONOS film, as indicated by the arrow in the figure. Reference numeral 800 indicates generation of carriers due to impact ionization. The generated electron and hole, carriers, are indicated by a white circle and a shaded circle, respectively. This phenomenon is known as source side injection (SSI) and has been reported by, for example, A. T. Wu et al. (1986 IEEE International Electron Device Meeting, Technical Digest, 1986, p. 584-587 (Nonpatent Document 4)). The technique described above is directed to floating-gate memory cells. However, the injection mechanism also applies to “insulator film type” memory cells. This type of hot electron injection is characterized in that since the electric field is concentrated around the boundary between the select gate and the memory gate, the injection occurs predominantly at the select gate side portion of the memory gate. Further, unlike floating gate memory in which the charge retention layer is formed of electrodes, “insulator film type” memory retains charge within an insulating film. This means that in the case of “insulator film type” memory, electrons are retained within a very narrow region.
(2) FIG. 4 schematically shows an erase operation. A negative potential is applied to the memory gate 550 and a positive potential is applied to the diffusion layer electrode 200 on the memory gate side to cause strong inversion at the overlap between the memory gate and the diffusion layer. This leads to band-to-band tunneling, generating holes, as indicated by reference numeral 810 in the figure. Band-to-band tunneling is described by, for example, T. Y. Chan et al. (1987 IEEE International Electron Device Meeting, Technical Digest, p. 718-721 (Nonpatent Document 5)). In this memory cell, the generated holes are accelerated in the channel direction, attracted toward the memory gate by its bias, and thereby injected into the MONOS film, resulting in an erase operation. Reference numeral 820 indicates an electron-hole pair generated by a generated hole. These carriers are also injected into the MONOS film. That is, the threshold voltage of the memory gate that has been increased due to the negative charge of the injected electrons can be lowered by the positive charge of injected holes.
(3) When the memory cell is in the data retention state, the charge carriers injected into the MONOS insulating film are retained therein. Carriers move very little and very slowly within the insulating film, which allows them to be reliably retained without applying a voltage to the electrodes.
(4) When a read operation is performed on the memory cell, a positive potential is applied to the diffusion layer electrode 300 on the select gate side and a positive potential is applied to the select gate 500 to set the channel under the select gate to an “on” state. In this state, the data retained in the form of charge can be read as a current by applying a memory gate potential intermediate between the threshold voltages in the program or write and erase states.
[Patent Document 1]
U.S. Pat. No. 5,969,383
[Patent Document 2]
U.S. Pat. No. 6,477,084
[Nonpatent Document 1]
S. Sze, “Physics of Semiconductor Devices, 2nd edition, Wiley-Interscience pub., p. 496-506
[Nonpatent Document 2]
S. Sze, “Physics of Semiconductor Devices”, 2nd edition, Wiley-Interscience pub., p. 447
[Nonpatent Document 3]
1997 Symposium on VLSI Technology, 1997, p. 63-64
[Nonpatent Document 4]
1986 IEEE International Electron Device Meeting, Technical Digest, 1986, p. 584-587
[Nonpatent Document 5]
1987 IEEE International Electron Device Meeting, Technical Digest, p. 718-721
[Nonpatent Document 6]
2001 IEEE International Electron Device Meeting, Technical Digest, p. 719-722